Continuing advances in the design of electronic circuits and circuit elements has led to a need for multichip packaging which provides high chip densities, shorter interconnections and higher yields. Multichip modules are used in high end computers and aerospace applications, and are also expected to be used in telecommunications and personal computer applications in the very near future. There is a need for multichip modules of even higher density and shorter interconnections.
U.S. Pat. No. 4,954,480 of Imanaka et al. issued Sep. 4, 1990, discloses a multi-layer superconducting circuit substrate, including insulating layers and interconnection patterns of a superconductive ceramic material located between the insulating layers. The patterns of the superconductive ceramic material are connected via through-holes.
The generally recognized procedure for preparing multilayer interconnect structures consists of the sequential deposition of layers by various physical and chemical deposition techniques. In order to provide good quality high temperature superconducting layers with sufficiently high critical current densities, it is expected that these high temperature superconducting layers and the other layers will have to be grown epitaxially. Sequential epitaxial deposition of multilayers is difficult, particularly in view of additional necessary constraints. For example, the materials must be chosen so that the coefficients of thermal expansion of all the materials are essentially the same and any dielectric materials used must also have the proper dielectric constant and low microwave loss.
This invention provides electrical interconnect structures comprised of high temperature superconducting signal layers having increased density and shorter interconnections. This invention also provides processes for making such structures which do not involve epitaxial deposition of all the layers, and thus do not have the severe constraints described above.